1. Technical Field
The present invention relates in general to testing electronic devices and, in particular, to testing integrated circuits. Still more particularly, the present invention relates to a method and system for wafer and device-level testing of integrated circuits such as memories.
2. Description of the Related Art
Integrated circuit memories, such as dynamic random access memories (DRAMs), are nearly universally utilized to provide data storage in electronic systems, such as computer systems. To ensure proper operation of the electronic systems, the manufacturing process for integrated circuit memories includes a number of testing steps intended to verify that the integrated circuit memories will provide reliable performance over the expected lifetime of the electronic systems in which they are installed.
A typical manufacturing process for DRAMs begins with the fabrication of a semiconductor wafer containing hundreds or even thousands of identical dice that each include integrated memory circuitry. The integrated memory circuitry in each die generally includes a memory array for storing data and may include interface circuitry for accessing the memory array and performing other operations in response to memory requests or commands.
Following wafer fabrication, a quick first pass wafer probe is performed in an attempt to identify dies on the wafer having defects. The first pass wafer probe, which is conventionally performed utilizing clock, address and data signals having lower than normal operating frequencies, writes and reads some or all memory locations to identify defective rows and columns in the memory array.
Because memory array defects are not uncommon, a typical DRAM die is fabricated with one or more redundant rows and columns that can be activated in place of defective rows and columns by redundancy fusing. Thus, if any defects are detected during the first pass wafer probe, redundancy fusing is performed (e.g., by application of high voltage or lasing) to repair the defects. Once any such redundancy fusing has been performed, the wafer is subjected to a second pass wafer probe to determine the efficacy of fusing in addressing detected defects, and any dies failing the second pass wafer probe are marked as faulty.
Following the second pass wafer probe, the wafer is scribed into dice. Dice marked as faulty after the wafer probes are discarded, and dice passing the wafer probes are packaged to obtain DRAM devices. Packaging technologies that are commonly used for DRAMs include, among others, ball grid array (BGA) and wire bond.
After packaging, the packaged DRAMs are subjected to device-level testing. Device-level testing, like the wafer probe tests, may include low frequency tests of the DRAM array. Device-level testing may also include a “burn-in” test in which the packaged DRAMs under test are subjected to high ambient temperatures and tests of long duration in order to discover early life failures. Device-level testing also differs from wafer probe testing in that, in addition to basic pattern testing of memory arrays, device-level testing generally tests the DC and AC characteristics of the packaged DRAMs and the logic and operation of the memory interface. Device-level testing also differs from wafer probe testing in that device-level testing is typically performed at or near the rated signal frequencies of the packaged DRAM, which generally requires more sophisticated and expensive test equipment.
Packaged DRAMs that pass the device-level test may subsequently be assembled together on circuit cards to form memory modules such as SIMMs (single in-line memory modules) and DIMMs (dual in-line memory modules). Each memory module is then typically subjected to a final, intensive fault test prior to shipping or installation. The faults detected by module testing include faults in the circuit cards themselves (e.g., open or shorted traces), faults introduced by module assembly (e.g., damaged pin drivers, open or shorted pins, and ESD damage), and undetected faults in the DRAM circuitry. Following completion of testing, DRAM devices and modules that pass can then be installed in an end-use application.
One drawback of the conventional DRAM manufacturing process outlined above is that a number of faults are not discovered until late in the manufacturing process, for example, during device-level and module testing. As appreciated by the present invention, if such defects could be detected earlier in the manufacturing process (i.e., during wafer testing), the significant expense associated with packaging and module assembly of the defective dice could be eliminated. Unfortunately, the expense of the sophisticated test equipment currently required to fully exercise integrated memory circuitry prohibits its use during wafer testing.
A second drawback of the conventional manufacturing process is that several different pieces of specialized test equipment are required to fully test many integrated circuits. For example, to test the memory array of a DRAM, an algorithmic tester is utilized to write a predetermined data pattern into the memory array, read out the contents of the memory array, and then compare the output data with the original data pattern. A separate vector tester is utilized to exercise the memory's internal test logic, such as that defined in the IEEE 1149.1 standard. A third system tester is also employed to verify proper operation of the DRAM in response to commands. As will be appreciated, the use of multiple testers compounds the expense of testing.
A third drawback of the prior art is that conventional test equipment does not fully emulate the intended end-use environment of devices under test. In particular, conventional testers for packaged DRAM devices and modules have a fixed input impedance. This input impedance cannot be adjusted and may result in test behavior that is quite different from the operating behavior of the DRAM device under test when it is eventually installed in an end-use environment. Consequently, there may be an unacceptably high number of faulty devices or modules that pass the test process and even some satisfactory devices that fail the test process.